By Himanshu Bhatnagar
Complex ASIC Chip Synthesis: utilizing Synopsys TM layout CompilerTM actual CompilerTM and PrimeTime TM, moment variation describes the complicated options and methods used in the direction of ASIC chip synthesis, actual synthesis, formal verification and static timing research, utilizing the Synopsys suite of instruments. furthermore, the total ASIC layout stream method specified for VDSM (Very-Deep-Sub-Micron) applied sciences is roofed intimately.
The emphasis of this booklet is on real-time software of Synopsys instruments, used to strive against a variety of difficulties visible at VDSM geometries. Readers might be uncovered to an efficient layout technique for dealing with advanced, sub-micron ASIC designs. value is put on HDL coding types, synthesis and optimization, dynamic simulation, formal verification, DFT experiment insertion, hyperlinks to structure, actual synthesis, and static timing research. At every one step, difficulties on the topic of each one section of the layout circulate are pointed out, with recommendations and work-around defined intimately. moreover, an important matters regarding format, inclusive of clock tree synthesis and back-end integration (links to format) also are mentioned at size. in addition, the booklet comprises in-depth discussions at the foundation of Synopsys know-how libraries and HDL coding types, special in the direction of optimum synthesis resolution. goal audiences for this publication are working towards ASIC layout engineers and masters point scholars project complicated VLSI classes on ASIC chip layout and DFT concepts.
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Additional info for Advanced ASIC chip synthesis: using Synopsys Design Compiler, Physical Compiler, and PrimeTime
Also, it must be noted that the entire ASIC flow is extremely iterative and one should not assume that the process described in this chapter is suitable for all designs. Later chapters discuss each topic in detail that can be tailored to your designs and methodology. 1 Example Design The best way to start this topic is to go through the whole process on an example design. v The top level of the design is called tap_controller which instantiates three modules called tap_bypass, tap_instruction and tap_state.
It must be noted that gross hold-time violations should be fixed at the pre-layout level, in order to minimize the number of hold-time fixes, which may result after the layout. sdf The above PT script performs the static timing analysis for the tap_controller design. Notice that the clock latency and transition are fixed in the above example, because at the pre-layout level the clock tree has not been inserted. Therefore, it is necessary to define a certain amount of delay that approximates the final delay associated with the clock tree.
Tape out after LVS and DRC verification. Figure 1-1, graphically illustrates the typical ASIC design flow discussed above. The acronyms STA and CT represent static timing analysis and clock tree respectively. DC represents Design Compiler. 1 Specification and RTL Coding Chip design commences with the conception of an idea dictated by the market. These ideas are then translated into architectural and electrical specifications. The architectural specifications define the functionality and partitioning of the chip into several manageable blocks, while the electrical specifications define the relationship between the blocks in terms of timing information.